(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form capacitor structures for a dynamic random access memory (DRAM), device.
(2) Description of Prior Art
The reduction in DRAM cell size has limited the horizontal dimension of DRAM capacitor structures, thus adversely influencing the ability of the semiconductor industry to continually increase DRAM capacitance via use of wide capacitor structures. The use of capacitor structures featuring crown shaped, or fin shaped configurations, has allowed a portion of the desired capacitance increases to still be realized, however the shrinking dimensions of the underlying DRAM transfer gate transistors limit the horizontal dimensions of these capacitor structures, and thus limit capacitor surface area. Thus efforts have been directed at increasing capacitor surface area, via novel fin type capacitor configurations.
Vertical stacked capacitor structures featuring multiple horizontal fin type features, extending horizontally from a vertical capacitor feature that is used to contact an underlying storage node plug structure, has allowed the surface area of the capacitor structure to be increased thus increasing DRAM capacitance. This invention however will describe a process for fabricating a DRAM capacitor structure, comprised with alternate fin type structures, offering increased capacitor surface area, and using less horizontal space, when compared to counterpart, non-alternate fin type capacitor structures. The novel alternative fin type capacitor structure, described in this invention, is comprised of two storage node features, each located in a storage node opening, formed in a stack of composite insulator layers, each overlying and contacting a storage node plug structure. However each storage node opening is defined in the composite insulator layers, with each opening featuring lateral recesses in specific components of the composite insulator layers. The lateral recesses for a first storage node opening are formed in first type components of the composite insulator layers, while the lateral recesses in the second storage node opening are formed in second components of the composite insulator layers. Thus a storage node structure formed in these storage node openings, is comprised of intertwining features, located in the lateral recesses of the storage node openings. The subsequent capacitor structure is therefore comprised with alternate fin type, storage node structures, providing increased surface area in less horizontal space, when compared to counterpart non-alternate fin type structures. Prior art, such as Sandhu, in U.S. Pat. No. 6,133,600, as well as Takaishi, in U.S. Pat. No. 5,903,430, describe methods of fabricating fin type, capacitor structures, however these prior arts do not describe the novel process described in this present invention in which alternate type, DRAM capacitor structures are formed featuring lateral recesses, formed in specific components of a composite insulator layer.
It is an object of this invention to increase the surface area of a DRAM capacitor via use of an alternate, fin type capacitor configuration.
It is another object of this invention to define a first storage node opening in a group of composite insulator layers, then selectively form lateral recesses in first components of the composite insulator layers, followed by definition of a second storage node opening in the same group of composite insulator layers, then selectively form lateral recesses in second components of the composite insulator layers.
It is yet another object of this invention to form a storage node structure, located in the first, and in the second storage node openings, with the storage node structure featuring horizontal, fin type components, located in the lateral recesses of the storage node openings, and with the fin type features in the lateral recesses in the first storage node opening, intertwined with the fin type features in the lateral recesses in the second storage node opening.
In accordance with the present invention a method of fabricating an alternate fin type, DRAM capacitor structure, featuring intertwined storage node structures, is described. After formation of storage node plug structures, contacting source/drain regions of underlying DRAM transfer gate transistors, a series of composite insulator layers, each comprised with a layer of silicon nitride, silicon oxide, borophosphosilicate glass (BPSG), and silicon oxide, is deposited. A first storage node opening is formed in the series of composite insulator layers, exposing the top surface of a first storage node plug structure, followed by lateral recesses selectively formed in the silicon nitride component of each composite insulator layer. A second storage node opening is then formed in the series of composite insulator layers, exposing a second storage node plug structure, followed by lateral recesses selectively formed in the BPSG component of each composite insulator layer. The lateral recesses in the first storage node opening, partially overlays the lateral recesses in the second storage node openings, with these lateral recesses separated by the silicon oxide component of the composite insulator layers. Storage node structures are then formed in the storage node openings, coating the lateral recesses in these openings, resulting in the intertwined horizontal fin type features. After formation of a capacitor dielectric layer on the storage node structures, a capacitor top plate is formed integrating the storage node structures, resulting in an alternate fin type, DRAM capacitor structure.